The present invention relates to trench MOSFET devices, and more particularly to trench MOSFET devices having symmetric current-voltage characteristics.
MOSFET (metal oxide semiconductor field effect transistor) technology advances have led to the development of a variety of transistor structures.
A conventional MOSFET structure is shown in FIG. 1A. This structure contains a P-type body region 102 with P+ contact region 103, a source region 104, a drain region 106 and a gate region, which consists of a doped polycrystalline silicon (polysilicon) conductive region 108 and a gate dielectric layer 109. An insulating layer 110 is provided over the conductive region 108. The electrical symbol of this structure is shown in FIG. 1B. This transistor has four terminals and has symmetric current versus voltage characteristics when the source and drain contacts are interchanged.
Another version of a MOSFET, known as a silicon-on-insulator (xe2x80x9cSOIxe2x80x9d) MOSFET, is illustrated in FIG. 2A. This transistor has a similar structure to that of FIG. 1A, with P-type body region 202, source region 204, drain region 206, and a gate region consisting of a doped polysilicon conductive region 208 and a gate dielectric layer 209. An insulating layer 210 is provided over the conductive region 208. However, each transistor is formed on its own silicon island, so that it is electrically isolated by an insulator from all other transistors. The presence of an underlying layer of insulating material 211 provides this electrical isolation. Moreover, to increase device density, electrical contact is typically not made to the body region of the SOI MOSFET. The electrical symbol of this structure is shown in FIG. 2B. SOI MOSFETs, like conventional MOSFETs, have symmetric current versus voltage characteristics when the source and the drain regions are interchanged.
The electrical characteristics of the above conventional MOSFET and SOI MOSFET, however, differ in one significant fashion. The drain-to-source breakdown voltage of the conventional MOSFET will be affected by the voltage on its body region. When the body region is electrically shorted to the source region, the drain-to-source breakdown voltage, or BVDSS, of the conventional MOSFET is equal to the collector-to-base breakdown voltage, BVCBO, of the bipolar transistor that is intrinsic to the device. When the body region is not electrically connected at all (i.e., it is allowed to xe2x80x9cfloatxe2x80x9d), the BVDSS of the conventional MOSFET is equal to the collector-to-emitter breakdown voltage, BVCEO, of the intrinsic bipolar transistor. The BVCEO of a conventional MOSFET is related to its BVCBO by the following equation (taken from Grove, Andrew S., Physics and Technology of Semiconductor Devices, John Wiley and Sons, 1967, p. 233):       BV    CEO    =            BV      CBO                      β        +        1            η      
Where xcex7 is a number with a value in the range of 4 for an npn transistor and xcex2 is the current gain of the transistor.
This equation indicates that a conventional MOSFET transistor with its body electrically floating has a lower breakdown voltage than the corresponding transistor with its body shorted to its source. Similarly, an SOI MOSFET, with its floating body region, has a lower breakdown voltage than it would have if its body were connected to its source. See, S. Cristoloveanu, xe2x80x9cSOI, a Metamorphosis of Siliconxe2x80x9d, IEEE Circuits and Devices, Jan. 1999, pp. 26-32.
A double-diffused MOSFET, also known as a DMOS transistor, is another popular transistor structure. FIG. 3A illustrates a vertical DMOS transistor, which is provided with (a) P/P+ body regions 302, (b) N+ source regions 304, (c) gate regions of conductive doped polysilicon 308 and gate dielectric layer 309, with insulating layer 310 provided over the polysilicon 308, and (d) a common N-type drain region 306, all disposed over an N+ substrate 307. The polysilicon regions 308 are typically extended into a region outside the active area, where a common metal gate contact is provided. As can be seen from this figure, the P-type body regions 302 are shorted to the N+ source regions 304 thorough source metal 303. The electrical symbol of this structure is shown in FIG. 3B.
A variation of the vertical DMOS transistor of FIG. 3A is the trench DMOS transistor, illustrated in FIG. 4A, which includes (a) P/P+ body regions 402, (b) N+ source regions 404, (c) gate regions of conductive doped polysilicon 408 and gate dielectric layer 409, with insulating layer 410 provided over the polysilicon 408, and (d) a common N-type drain region 406, all disposed over an N+ substrate 407. In this structure, carrier flow between the source regions and the drain region occurs along the vertical sidewalls of trenches within the structure. The doped polysilicon 408 portions of the gate are separated from the channel regions within body regions 402 by gate dielectric 409 portions. Carrier flows from the source regions 404 to the drain region 406 when a sufficiently large gate-to-source voltage is applied (which creates the channel in body regions 402) and a drain-to-source voltage is present. The electrical symbol of this structure is shown in FIG. 4B.
DMOS transistors are used for high current and/or high voltage applications, because the DMOS structure provides at least the following advantages when compared to, for example, the conventional MOS structure of FIG. 1A:
(1) The channel length is set by the difference in the dopant profiles, which are formed by the sequential diffusion of the body and source regions from the same edge (i.e., from the upper surface). As a result, the channel length (L) can be quite short, resulting in a relatively high value of W/L per unit of surface area, where W is the amount of source perimeter. A high W/L value per unit of surface area is indicative of a high-current density device.
(2) The body-to-drain depletion region spreads in the direction of the drain, rather than into the channel region, resulting in higher breakdown voltages.
The current-versus-voltage curves of the vertical DMOS transistor of FIG. 3A and of the trench DMOS transistor of FIG. 4A are asymmetric due to the source-to-body diode that is present within the structures. For many applications, this asymmetry is not a factor. However, there are some applications where a symmetric characteristic is required. In such applications, two DMOS transistors with sources electrically connected together (and sometimes gates as well) are used, as shown schematically in FIG. 5. Unfortunately, the use of two DMOS transistors in series to form a bilateral switch requires significantly greater area than a single DMOS transistor having the same on-resistance.
The present invention addresses the above and other challenges in the prior art by providing a trench MOSFET transistor with symmetric current-voltage characteristics.
According to an embodiment of the invention, a trench MOSFET transistor device is provided which comprises: (a) a drain region of first conductivity type; (b) a body region of a second conductivity type provided over the drain region, such that the drain region and the body region form a first junction; (c) a source region of the first conductivity type provided over the body region, such that the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising: (i) an insulating layer, which lines at least a portion of the trench and (ii) a conductive region, which is disposed within the trench adjacent the insulating layer. The body region in this device is separated from the source metal. Moreover, the doping profile within the body region and within at least a portion of the source and drain regions, when taken along a line normal to upper and lower surfaces of the device, is such that the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.
According to another embodiment of the invention, a trench MOSFET transistor device is provided, which comprises: (a) a silicon drain region of N-type conductivity; (b) a silicon body region of P-type conductivity provided over the drain region, wherein the drain region and the body region form a first junction; (c) a silicon source region of N-type conductivity provided over the body region, wherein the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising: (i) a silicon dioxide layer lining at least a portion of the trench and (ii) a doped polycrystalline silicon region disposed within the trench adjacent the silicon dioxide layer. Within this device: (a) the body region is separated from the source metal by the source region, (b) the source and drain regions comprise the same doping material, (c) the source and drain regions have peak net doping concentrations that are greater than a peak net doping concentration of the body region, and (d) the doping profile taken along a line normal to upper and lower surfaces of the device is such that, within the body region and within at least a portion of the source and drain regions, the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.
According to another embodiment of the invention, a method of forming a trench MOSFET transistor device is provided which comprises: (a) providing a drain region of first conductivity type; (b) providing a body region of a second conductivity type over the drain region, the drain region and the body region forming a first junction; (c) providing a source region of the first conductivity type over the body region, the source region and the body region forming a second junction; (d) forming a trench that extends through the source region, through the body region and into the drain region; (e) forming an insulating layer over at least a portion of the trench; (f) providing a conductive region within the trench adjacent the insulating layer; and (g) providing source metal on an upper surface of the source region. This method is performed such that (i) the body region is separated from the source metal, and (ii) a doping profile along a line normal to upper and lower surfaces of the device is established in which, within the body region and within at least a portion of the source and drain regions, the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.
In some embodiments, for example, the body region and the source region are formed prior to trench formation. In others, the body region is formed before trench formation and the source region is formed after trench formation. Various embodiments are available for forming the drain, body and source regions.
One advantage of the present invention is that a single MOSFET transistor with symmetric current-voltage characteristics is produced. This design requires significantly less surface area than a design based on two MOSET transistors in series.
The above and other embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon review of the following.